Wireless Communication Device and Data Interface

ABSTRACT

A wireless communication device comprises a number of sub-systems operably coupled to a data interface for routing data between the number of sub-systems. A clock generation function generates a clock signal substantially at a data transfer rate to be used over the data interface whereby the clock signal is generated at a rate that minimises harmonic content of the clock signal at operational frequencies of the wireless communication device. Thus, a suitable data rate is selected and supported by the data interface that accommodates the desired bandwidth, clock rate and/or chip rate of the functional elements that are coupled by the data interface within the wireless communication device, whilst minimising the effects of harmonic interference from the clock signal(s).

FIELD OF THE INVENTION

This invention relates to a data interface for a wireless communicationsdevice. The invention is applicable to, but not limited to, datainterfaces for multimode wireless communication devices.

BACKGROUND OF THE INVENTION

Wireless communication devices, such as mobile phone handsets, require avery high level of integration of hardware and firmware/software inorder to achieve the necessary density of functionality, i.e. to realisethe necessary functionality in a minimum device volume and at a minimumcost. An optimal wireless communication device design must also minimisepower consumption in order to increase the battery call time and/orstand-by time.

Wireless communication devices also incorporate a number of distinct andoperably coupled sub-systems, in order to provide the wide variety offunctions and operations that a complex wireless communication deviceneeds to perform. Such sub-systems comprise radio frequency poweramplification functions, radio frequency integrated circuits (RFIC)comprising radio frequency generation, amplification, filtering, etc.functions, baseband integrated circuits (BBIC) comprising audiocircuits, encoding/decoding, (de)modulation functions, processingfunctions, etc. and memory units.

Interfaces, which are often standardised to allow commonality andincreased functionality between different chip-set manufacturers anddifferent handset manufacturers, are defined for communicating betweenthe respective sub-systems.

One typical interface found in a wireless communication device is theinterface between a baseband integrated circuit (BBIC) and a radiofrequency integrated circuit (RFIC). Pins on ICs are used to routeelectrical signals between devices/elements/functions. It is generallydesirable to minimise the number of pins in ICs used in wirelesscommunication devices, as the use of extra pins, for example on aBBIC-RFIC interface, increases IC area, increases IC cost and complexityand increases power consumption.

In the field of mobile phones, a consortium of mobile phonemanufacturers has been formed to define various sub-system interfaces,particularly interfaces between variants of second generation ofcellular phones (2.xG) when migrating to cover additional, futurewireless communication technologies, such as multimode transceiversadditionally employing third generation (3G) wideband code divisionmultiple access (WCDMA) technology. This consortium is known as ‘DigRF’,and details of the defined interfaces and functionality thereof,particularly in a multimode mobile phone scenario, can be found on theirweb-site at www.digrf.com. It is noteworthy that Multimode operationalspecifications are not yet available at the time of filing this patentapplication.

One interface being defined by the DigRF consortium is the BB-RFinterface standard, which encompasses a serial data interface forReceive (Rx) and Transmit (Tx) variants of second generation of cellularphones (2.xG) chipsets. When defining the interface to also accommodatethe increased complexity and data rate required for 3G technology, it isclearly advantageous to minimise the IC pin count.

Furthermore, the standardised RFIC-BBIC interface for the current 2.xGmobile phone products does not provide for simultaneous Rx and TX datatransfer to the RFIC. Although, providing such a simplex operation isacceptable in a 2G environment and 2G variants thereof, thecorresponding limited bandwidth is not sufficient for 3G Rx or Txoperation.

Additionally, the standardised system clock frequency used in 20 mobilephones (SysClk) is defined as 26 Mhz. This frequency sets a useful datarate for 2.xG modes of operation. For 30 operation, it is not as usefulas it is not an integer multiple of the WBCDMA chip rate.

The inventors of the present invention have recognised and appreciatedthat a further problem exists with running data interfaces oil such aradio transceiver system (say between the RFIC and the BBIC) in that togenerate and decode random data patterns a clock source is required atthe data rate, or an integer multiple thereof. This clock source isuniform and therefore the harmonic content of the clock source will notbe spread.

Thus, a significant problem in the field of wireless communicationdevices is that the harmonic content power of clocks are known toradiate signals at frequencies that coincide with transmit and receivesignals of the transceiver.

Notably, the ‘DigRF’ 2G standard for use in global system for Mobiletelecommunications (GSM) standard mobile terminals has adopted a systemclock rate of 26 MHz on the data interface between the basebandintegrated circuit (IC) and the radio frequency (RF) IC. Notably, theuse of such a defined clock rate creates fourteen harmonics in the GSMquad-band Rx and Tx frequency bands, i.e. the four frequency bandsallocated for GSM in various regions of the world. This harmonic contentproblem generated by the clock signals running at 26 MHz requires radiotransceiver designers to use slew rate control clocks to limit thisproblem.

Furthermore, very careful layout of the printed circuit board for theICs used in the device is then required, to minimise the effect of theseharmonics. Thus, the selection of a particular clock rate has asignificant impact on the corresponding circuitry designed into thewireless communication device.

US patent—U.S. Pat. No. 6,737,904 B1—of Philips Electronics N.V.discloses a 2G phone BBIC that aims to address the problems associatedwith the GSM 26 MHz system clock. U.S. Pat. No. 6,737,904 B1 discloses amechanism of dynamically applying a random number generator to a 26 MHzclock signal to introduce jitter, and therefore introduce phase changesto the clock signal in order to spread noise.

A further solution to harmonic interference (purely and notably in a 2Genvironment) has been proposed in WO2002056488A2, inventor of Tuttle et.al. and titled Digital Interface Apparatus and Associated methods. InWO2002056488A2 suppression of interference between 2G ICs is performedusing band limiting single-ended circuits and differential signals andan optimum die partition within the RF sub-system.

A further solution to harmonic interference, in the context of liquidcrystal displays, is proposed in U.S. Pat. No. 6,720,943 B1, inventorKim et. al. and titled Data Interface device. U.S. Pat. No. 6,720,943 B1proposes to spread the electro-magnetic interference (EMI) by means of aclock dithering mechanism.

A problem associated with the clock dithering mechanism proposed in U.S.Pat. No. 6,720,943 B1 is that clock dithering spreads the noise butreduces the reliability of the data link. The use of a clock ditheringmechanism creates a further problem in that there is increased hardwareoverhead. Dither needs to be random so as not to generate new tones.Thus, this technique attempts to reduce the contribution of harmonicnoise to an RE sub-system, but fails to minimise or eliminate theharmonic noise.

Thus, existing solutions to clock harmonics attempt to ‘reduce’ theimpact of the harmonic, predominantly by dithering the clock signal tospread the noise. A need therefore exists for a mechanism to incorporateintegrated circuits/sub-systems and a corresponding data interface,within a wireless communications device, without incurring increasedcost or complexity or increased pin count whilst minimising oreliminating the effects of harmonic interference of the clock signal(s).

STATEMENT OF INVENTION

In accordance with aspects of the present invention, there is provided adata interface, a wireless communication device and an integratedcircuit therefor as defined in the appended Claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will now be described, byway of example only, with reference to the accompanying drawings, inwhich:

FIG. 1 illustrates a simplified block diagram of a wirelesscommunication device, illustrating a BBIC-RFIC interface as defined bythe DigRF 2.xG standard, adapted in accordance with the preferredembodiment of the present invention;

FIG. 2 shows a graph illustrating a number of harmonic interferers(measured in the Release 5 (2.xG and 3G) frequency bands set by the 3GPartnership Project) versus data rate (from 26 to 500 Mbits/sec);

FIG. 3 shows a graph illustrating a number of Harmonic interferers(measured in the Release 5 (2.xG and 3G) frequency bands set by the 3GPartnership Project) versus data rate (from 188 to 212 Mbits/sec);

FIG. 4 illustrates a clock sequence power spectral density (PSD) graphof the 199.68 Mhz clock rate used in the preferred embodiment of thepresent invention;

FIG. 5 illustrates a schematic block diagram of a BBIC-RFIC andassociated data interface operating a 1248 MHz clock and 199.68 Mbpsdata stream in accordance with a first embodiment of the presentinvention; and

FIG. 6 illustrates a schematic block diagram of a BBIC-RFIC andassociated data interface operating a 199.68 MHz or a multiple of1-99.60 MHz clock and 1-99.68 Mbps data stream in accordance with asecond embodiment of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

The preferred embodiment of the present invention will be described interms of a wireless communication device, such as a multimode 3G-2.xGmobile telephone. However, it will be appreciated that the invention maybe embodied in any other type of wireless communication device thatincorporates a data interface between respective sub-systems within thedevice.

Referring first to FIG. 1, there is shown a simplified block diagram ofpart of a wireless communication device 100, adapted to support theinventive concepts of the preferred embodiments of the presentinvention. The wireless communication device 100, in the context of thepreferred embodiment of the invention is a multimode 3G-2.xG mobiletelephone. As such, the wireless communication device 100 contains anantenna 135, preferably coupled to a 3G duplex filter or 2.xG antennaswitch 140, that provides isolation between receive and transmit chainswithin the wireless communication device 100. The receiver chain, asknown in the art, includes numerous receiver circuitries such asreceiver front-end circuitry effectively providing reception, filteringand intermediate or base-band frequency conversion. The receivercircuitry is preferably predominantly formed on a radio frequencyintegrated circuit (RFIC) 120. The RFIC 120 is preferably coupled to anumber of other elements/functions (not shown) such as signal processingfunctions, memory elements, etc.

As known in the art, the RFIC 120 is operably coupled to a baseband IC(BBIC) 110 that performs a number of signal processing operations atbaseband frequencies, such as decoding/encoding, (de)modulation,(de-)interleaving functions and the like. The BBIC 110 is preferablycoupled to a number of other elements/functions (not shown) such assignal processing functions, memory elements, etc. The BBIC 110preferably comprises a timer or clock function (not shown), or isoperably coupled to an external timer or clock, to control the timing ofoperations (transmission or reception of time-dependent signals) withinthe wireless communication device 100.

The coupling between the RFIC 120 and the BBIC 110 is preferablyimplemented via a RFIC-BBIC data interface 105, which comprises eightpins to carry electrical signals therebetween. The eight pins preferablycomprise a RxTxdata line 111, a RxTxEn line 112, a CtrlData line 113, aCtrlEn line 114, a CtrlClk line 115, a Strobe line 116, a SysClk line117 and a SysClkEn line 118.

It is envisaged that the BBIC 110 may be operably coupled to a pluralityof RFICs 120 (not shown), where each RFIC has, say, a separate CtrlEnline 114 and a SysClkEn line 118. The BBIC is also preferably coupled toone or more output devices, such as audio speaker 160 and/or display170.

As regards the transmit chain of the wireless communication device 100,this includes an input device, such as a microphone 150 and/or keypad(not shown), coupled to the BBIC 110. The RFIC in a transmit function iscoupled to a radio frequency power amplifier 125 and thereafter to theantenna 135 via the antenna switch or duplex filter 140. A batteryregulator (not shown) associated with the RFIC 120 is preferably undercontrol of a power management unit 130, with the BBIC 110 maintainingcontrol of the power management unit 130.

In accordance with the preferred embodiment of the present invention,the BBIC-RFIC interface, and therefore the BBIC and RFIC devices, havebeen adapted to function at a particular data rate that minimisesharmonic interference at the frequencies transmitted from, or receivedto, the antenna 135. The preferred configurations of the RFIC-BBIC anddata interface are further described with reference to FIG. 5 and FIG.6.

Referring now to FIG. 2 and FIG. 3, two graphs 200, 300 illustrate anumber of harmonic interferers (where the analysis is directed to theRelease 5 frequency bands controlled by the 3G Partnership Project(3GPP)) versus data rate (from 26 to 500 Mbits/sec in FIG. 2 and from188 to 212 Mbits/sec in FIG. 3).

The y-axis 210, 310 illustrates the number of harmonic interferersfalling on the aforementioned 3GPP Rx or Tx bands using a variety ofclock rates 220, 320 as shown on the x-axis. Notably, in FIG. 3 theinventors of the present invention have identified a small frequencyband close to 200 Mhz where no harmonics of the selected clock ratewould fall on the critical 2.xG and 3G Rx or Tx bands. Thus, andadvantageously, by setting a clock rate of approximately 200 MHz for thedata interface to use, no harmonic interference of the 3GPP frequencieswill be generated by the clock signals.

For a 3G transceiver it is important that the clock rate employed overthe data interface be a multiple of the WBCDMA chip rate. The WBCDMAchip rate is 3.84 Mcs. A multiple of 3.84 Mcs is required for a singledata serial interface between an RF subsystem and BB subsystems. Hence,the inventors of the present invention have selected a multiple of 52times the 3G chip rate, i.e. a clock rate of 199.68 Mhz is used by theRFIC-BBIC data interface. Thus, the selection of a RFIC-BBIC clock rateof 199.68 Mhz facilitates accurate data transfer and data processingoperations of the wireless communication device, whilst effectivelyeliminating harmonic content of the clock signal within the 3GPP Release5 frequency bands.

Although the preferred embodiment of the present invention is describedwith respect to a serial data interface, it is envisaged that theinventive concepts apply equally to a parallel data interface.

FIG. 4 illustrates a graph 400 of a PSD (in dB) 410 of the 199.68 MHzclock signal versus frequency 420. It is noteworthy that the harmonicsof the 199.68 MHz clock signal 430 fall outside the Tx and Rx bands for2.xG and 3G 440, thereby alleviating the most difficult problem faced byradio transceiver designers. It is known that random data patterns ofsignals that are sent across the data interface spread the harmoniccontent of the data stream about the baud (symbol/bit rate). Thus, theharmonic content of the baud is also spread as a result.

It is desirable that the noise is spread over a wide bandwidth (BW).However, to recover data and transmit data, a clock source is requiredon each side of (or a clock signal is sent across) the interface.Harmonics of the clock signals are problematic due to theirconcentration of power at integer multiples of the clock in thefrequency domain, i.e. there is no spreading. This is therefore aproblem that needs resolving by the radio sub-system designer.

The PSD graph outlined in FIG. 4 illustrates the reasoning and harmonicinterference minimisation (effectively elimination) benefits ofselecting the 199.68 MHz interface for a 3G-2.xG multimode wirelesscommunication device.

Referring now to FIG. 5, a schematic block diagram of a BBIC-RFIC andassociated data interface operating a 1248 MHz clock source and a 199.68Mbps data stream is illustrated in accordance with a first embodiment ofthe present invention. Notably, the configuration illustrates amechanism where a higher frequency clock source is sent across theinterface where the clock frequency for the data transferred over theinterface is derived from this higher clock source. Still, the need togenerate a clock at the data rate is a requirement for data transfer onthe data interface.

The preferred configuration employs a hardware design that avoids theneed to incorporate a clock generation circuit at both sides of the datainterface, whereby the clock signal is also transferred across the datainterface. In this manner, the clock, or clock harmonics since the clockhas to be a relatively uniform signal, concentrates the harmonic powerat particular frequencies. However, it is envisaged that with some datainterface architectures, it may prove advantageous to employ a clocksource within each side of the data interface.

FIG. 5 illustrates a RFIC 510 operably coupled to a BBIC 550 across adata interface. The RFIC 510 comprises a 1248 MHz clock source 515,operably coupled to a first differential line driver 520. The 1248 MHzclock source 515 is operably coupled to a clock divider 525 to reducethe clock rate down to the desired 199.68 MHz rate. This clock rate isthen used for I-Q baseband data generation 535 for transferring dataover the data interface. The desired 199.68 MHz rate is also input to adata recovery function 545, which is preferably operably coupled tocontrol and transmit sub-systems (not shown).

The I-Q baseband data generation function 535 of the RFIC 510 isoperably coupled to a second differential line driver 530, to transmitI-Q data at 199.68 Mbps across the data interface. A differential buffer540 receives transmit information from the BBIC 550 to be passed to thedata recovery function 545 of the RFIC 510.

The BBIC 550 also comprises a first differential buffer 555 forreceiving the raw 1248 MHz clock signal. Again, in the BBIC 550, the1248 MHz clock signal is input to a clock divider 560 to reduce theclock rate down to the desired 199.68 MHz rate to be used for I-Qbaseband data recovery in function 570. The clock rate is used by theI-Q baseband data recovery function 570 to recover data received overthe data interface and buffered by BBIC second differential buffer 565.The data recovery function 570 outputs data that is re-synchronised andcan be output to a Rx processing feedback control function/sub-system(not shown).

An I-Q baseband data generation function 575 of the BBIC 550 is operablycoupled to a BBIC differential line driver 580, to transmit I-Q data at199.68 Mbps across the data interface. A differential line buffer 540 ofthe RFIC 510 receives I-Q data at 199.68 Mbits/sec from the I-Q basebanddata generation function 575 of the BBIC 550.

In this manner, a single clock source 515, selected to operate at aparticular clock rate of 1248 MHz, is used to generate I-Q data streamsin both the BBIC 550 and RFIC 510. Furthermore, the single clock source515 is used to implement data recovery in both the RFIC 510 and BBIC 550from data transmitted at the I-Q data rate of 199.68 Mbits/sec acrossthe data interface. The use of this I-Q data rate of 199.68 Mbits/secensures that the clock signals passed over the data interface do notgenerate any harmonics at any of the 3GPP frequencies transmit from, orreceived to, the wireless communication device. A skilled artisan willappreciate that the Cartesian I-Q data format could be changed to someother data format for example polar magnitude and phase format.

Advantageously, by incorporating further divider functions coupled tothe 1248 MHz clock source 515, the BBIC 550 and RFIC 510 are able togenerate other clock signals. For example, a clock divider of ‘divide by48’ coupled to the 1248 MHz clock source 515 would provide a clocksignal of 26 MHz, which is ‘96’ times the symbol rate of 2.xG, and aclock divider of ‘divide by 325’ coupled to the 1248 MHz clock source515 would provide a clock signal at the 3G chip rate of 3.84 MHz.

Referring now to FIG. 6, a second embodiment of the present invention isillustrated, whereby a RFIC 610 is operably coupled to a BBIC 650 acrossa data interface. The configuration of FIG. 6 is ideally suited toaccommodate a 3G wireless communication device that will also not createharmonic content of the clock signal at 2.xG or 3G frequencies. The RFICcomprises an N*199.68 MHz clock source 615, operably coupled to a datastream generation function 620 for generating a data stream at 199.68Mbits/sec. ‘N’ is defined preferably, but not necessarily, as aninteger, to provide an integer multiple of the clock signal.

The N*199.68 MHz clock rate is also input to a data recovery function635, which is preferably operably coupled to control and transmitsub-systems (not shown).

The Rx I-Q baseband data generation function 625 of the RFIC 610 isoperably coupled to a second differential line driver 630, to transmitI-Q data at 199.68 Mbps across the data interface. A differential buffer640 receives transmit information from the BBIC 650 to be passed to thedata recovery function 635 of the RFIC 610.

The BBIC 650 also comprises a first differential buffer 655 forreceiving the N4199.68 MHz, clock signal from the N*199.68 MHz clocksource 615. Again, in the BBIC 650, the N*199.68 MHz clock signal isused for I-Q baseband data recovery in function 660. The clock rate isused by the I-Q baseband data recovery function 660 to recover datareceived over the data interface and buffered by the BBIC seconddifferential buffer 665. The data recovery function 660, outputs datathat is re-synchronised and can be output to a Rx processing feedbackcontrol function/sub-system (not shown).

An I-Q baseband data generation function 670 of the BBIC 650 is operablycoupled to a BBIC differential line driver 675, to transmit I-Q data at199.68 Mbps across the data interface. A differential buffer 640 of theRFIC 610 receives I-Q data at 199.68 Mbits/sec from the I-Q basebanddata generation function 670 of the BBIC 650.

In this manner, a single clock source 615, selected to operate at aparticular clock rate of N*199.68 MHz, is used to generate I-Q datastreams in both the BBIC 650 and RFIC 610. Furthermore, the single clocksource 615 is used to implement data recovery in both the RFIC 610 andBBIC 650, from data transferred at the I-Q data of 199.68 Mbits/secacross the data interface. The use of this I-Q data rate of 199.68Mbits/sec ensures that the clock signals passed over the data interfacedo not generate any harmonics at any of the 3G frequencies transmitfrom, or received to, the wireless communication device.

The above two embodiments are not considered as the only arrangementscapable of utilising the inventive concepts described herein, as otherarchitectures may also be implemented that could benefit from aselection of a data rate to minimise harmonic interference. An exampleof such an architecture would be one based on encoders to encode thedata (at the transmitting side) at a data rate of 199.68 Mbits/sec and acorresponding decoder (at the receiving side) to likewise decode thereceived data at 199.68 Mbits/sec. Any number of differentencoder/decoder techniques could be used in such architecture, such asManchester encoders/decoders, as known in the art.

The inventive concepts hereinbefore described relate to generation of aclock rate of 199.68 Mbits/sec. However, it is within the contemplationof the present invention that variations of this frequency (or multiplesthereof) may still be used that fall within the tolerances of therequired data rates for one or more respective communication modes,whereby harmonics substantially fall outside of one or more respectivecommunication mode frequency bands. Furthermore, it is envisaged thatmultiples of the clock rate of 199.68 Mbits/sec may be used, where sucha configuration would still benefit from the inventive conceptsdescribed above.

Although the inventive concepts are described with reference to a lowvoltage differential signal (LVDS) type on the data interface, a skilledartisan will appreciate that other signalling types and data interfacesare able to utilise the inventive concepts employed herein, such as asingle-ended data interface. A skilled artisan will also appreciate thatthe clock source in the above embodiments may also be sourced from theBB IC (or another sub-system) in contrast to the RFIC shown.

Furthermore, although the inventive concepts are hereinbefore describedwith respect to generation of I-Q data, a skilled artisan willappreciate that the inventive concepts are equally applicable to anydata type, such as polar co-ordinate data, demodulated data, raw data,etc.

It will also be appreciated by a skilled artisan that although the aboveconcepts have been described with reference to a BBIC-RFIC interface,the inventive concepts are equally applicable to any data interface.Furthermore, it is envisaged that the inventive concepts are not limitedto a dual 3G-2-xG wireless communication device, but are applicable toany multimode wireless communication device, for example a wirelesscommunication device supporting Bluetooth™ or ultra wideband orthogonalfrequency division multiplex (UWB OFDM) technology.

It is envisaged that the aforementioned inventive concepts can beapplied to most transceiver architectures and platform solutions, i.e. asemiconductor manufacturer may employ the inventive concepts in a designof a stand-alone RFIC and/or BBIC and/or any other sub-system element.

It will be understood that the data interface and operation thereofdescribed above aims to provide one or more of the following advantages:

-   -   (i) A suitable data rate can be selected to be supported by the        data interface that accommodates the desired bandwidth, clock        rate and/or chip rate of the functional elements that are        coupled by the data interface;    -   (ii) The data rate is selected to avoid any harmonic        interference generated by any functional element coupled via the        data interface;    -   (iii) In the context of a 3G-2.xG multimode handset, the data        interface proposed herein enables 3G technology to be supported,        for example within the DigRF standard;    -   (iv) The use of 1248 MHz allows 2G/3G specific clocks to be        generated without harmonic interference;    -   (v) A clock rate of 199.68 Mbits/sec supports the required        bandwidth of communication between a BBIC and a RFIC in a 3G        implementation; and    -   (vi) The concepts allow a single clock source to be used for the        RFIC and BBIC and/or any other sub-system.

Thus, the present invention provides a number of advantages over currentwireless communication devices incorporating data interfaces. In thecontext of a mobile phone, the provision of a data interface operatingat a data transfer rate in the above manner, for example between a RFICand a BBIC at an integer multiple of the 3G WBCDMA chip rate,effectively eliminates (or at least minimises) harmonic problems. Inparticular, in a 2.xG-3G scenario, the proposed solution providesharmonics that fall outside the 3G and 2.xG spectrum occupancy.

Furthermore, the proposed data interface allows a reduction in volume,cost and power consumption of the wireless device, when compared tocurrent solutions, thus providing significant advantage to IC andwireless communication device manufacturers. Additionally, the proposeddata interface also solves the issue of minimising pin count on theinterface as both ‘I’ and ‘Q’ data, which can be sent separately for Txand Rx operations, can now be multiplexed on to the same data stream.

Whilst the specific and preferred implementations of the embodiments ofthe present invention are described above, it is clear that one skilledin the art could readily apply variations and modifications of suchinventive concepts.

Thus, a means of incorporating a data interface between integratedcircuits (or sub-systems) in a wireless communication device has beendescribed, where the aforementioned disadvantages with prior artarrangements, which need to accommodate interference due to clockharmonics, have been substantially alleviated.

1. A wireless communication device comprises: a number of sub-systemsand a data interface operably coupled to sub-systems for routeing datatherebetween; the wireless communication device further comprising aclock generation function that generates a clock signal substantially ata data transfer rate to be used over the data interface, wherein thewireless communication device is characterised in that the clockgeneration function comprises a clock source operably coupled to a clockdivider function for dividing the clock rate to substantially 199.68 MHzto be used for baseband data generation to generate data fortransferring over the data interface, thereby generating a clock signalat a rate that minimises harmonic content of the clock signal atoperational frequencies of the wireless communication device.
 2. Awireless communication device according to claim 1 further characterisedin that the number of sub-systems comprise a radio frequency integratedcircuit and/or a baseband integrated circuit.
 3. A wirelesscommunication device according to claim 1 further characterised in thata baseband data generation function is operably coupled to the clockgeneration function to generate data for transferring over the datainterface substantially at the clock signal rate.
 4. A wirelesscommunication device according to claim 1 further characterised in thatthe clock generation function is located in one or more sub-systemsoperably coupled to the data interface.
 5. A wireless communicationdevice according to claim 1 further characterised in that the higherclock source rate is also sent across the data interface.
 6. A wirelesscommunication device according to claim 5 further characterised in thatthe clock source generates approximately a 1248 MHz clock.
 7. A wirelesscommunication device according to claim 6 further characterised in thatthe clock source and/or reduced clock rate are substantially multiplesof the 1248 MHz clock or the 199.68 MHz data rate.
 8. A wirelesscommunication device according to claim 3 further characterised in thatthe baseband data generation function and the clock generation functionare operably coupled to one or more differential line driver(s) and/orone or more differential buffer(s) to support data transfer over adifferential line data interface.
 9. A wireless communication deviceaccording to claim 1 further characterised in that the wirelesscommunication device is a multimode wireless communication device andthe clock signal is generated at a rate that minimises harmonic contentof the clock signal at operational frequencies in a plurality ofoperation modes.
 10. A wireless communication device according to claim9 further characterised in that the multimode operation comprises thirdgeneration and one or more variants of second generation mobiletelecommunications.
 11. An integrated circuit for use in a wirelesscommunication device comprising: a baseband data generation function; aclock generation function operably coupled to the baseband datageneration function; and a plurality of ports operably coupled to a datainterface for routeing data generated by the baseband data generationfunction within the wireless communication device; wherein the clockgeneration function comprises a clock source operably coupled to a clockdivider function for dividing the clock rate to substantially 199.68 MHzto be used for baseband data generation for transferring over the datainterface, thereby generating a clock signal at a rate that minimisesharmonic content of the clock signal at operational frequencies of thewireless communication device.
 12. An integrated circuit according toclaim 11 further characterised in that the integrated circuit is a radiofrequency integrated circuit or a baseband integrated circuit.
 13. Anintegrated circuit according to claim 11 further characterised in thatthe higher clock source rate is also sent across the data interface. 14.An integrated circuit according to claim 13 further characterised inthat the clock source generates approximately a 1248 MHz clock.
 15. Anintegrated circuit according to claim 14 further characterised in thatthe clock source and/or reduced clock rate are substantially multiplesof the 1248 MHz clock or the 199.68 MHz data rate.